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FEATURES 34 MHz Full Power Bandwidth 0.1 dB Gain Flatness to 8 MHz 72 dB Crosstalk Rejection @ 10 MHz 0.03 /0.01% Differential Phase/Gain Cascadable for Switch Matrices MIL-STD-883 Compliant Versions Available APPLICATIONS Video Routing Medical Imaging Electro Optics ECM Systems Radar Systems Data Acquisition
4 x 1 Wideband Video Multiplexer AD9300
FUNCTIONAL BLOCK DIAGRAM (Based on Cerdip)
GENERAL DESCRIPTION
The AD9300 is a monolithic high speed video signal multiplexer usable in a wide variety of applications. Its four channels of video input signals can be randomly switched at megahertz rates to the single output. In addition, multiple devices can be configured in either parallel or cascade arrangements to form switch matrices. This flexibility in using the AD9300 is possible because the output of the device is in a high-impedance state when the chip is not enabled; when the chip is enabled, the unit acts as a buffer with a high input impedance and low output impedance. An advanced bipolar process provides fast, wideband switching capabilities while maintaining crosstalk rejection of 72 dB at 10 MHz. Full power bandwidth is a minimum 27 MHz. The device can be operated from 10 V to 15 V power supplies. The AD9300K is available in a 16-pin ceramic DIP and a 20-pin PLCC and is designed to operate over the commercial temperature range of 0C to +70C. The AD9300TQ is a hermetic 16-pin ceramic DIP for military temperature range (-55C to +125C) applications. This part is also available processed to MIL-STD-883. The AD9300 is available in a 20-pin LCC as the model AD9300TE, which operates over a temperature range of -55C to +125C. The AD9300 Video Multiplexer is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9300/883B data sheet for detailed specifications.
PIN DESIGNATIONS DIP LCC and PLCC
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
AD9300-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter (Conditions) INPUT CHARACTERISTICS Input Offset Voltage Input Offset Voltage Input Offset Voltage Drift2 Input Bias Current Input Bias Current Input Resistance Input Capacitance Input Noise Voltage (dc to 8 MHz) TRANSFER CHARACTERISTICS Voltage Gain3 Voltage Gain3 DC Linearity4 Gain Tolerance (VIN = 1 V) dc to 5 MHz 5 MHz to 8 MHz Small-Signal Bandwidth (VIN = 100 mV p-p) Full Power Bandwidth 5 (VIN = 2 V p-p) Output Swing Output Current (Sinking @ = +25C) Output Resistance DYNAMIC CHARACTERISTICS Slew Rate6 Settling Time (to 0.1% on 2 V Output) Overshoot To T-Step7 To Pulse8 Differential Phase9 Differential Gain9 Crosstalk Rejection Three Channels10 One Channel11 SWITCHING CHARACTERISTICS 12 AX Input to Channel HIGH Time13 (tHIGH) AX Input to Channel LOW Time 14 (tLOW) Enable to Channel ON Time 15 (tON) Enable to Channel OFF Time 16 (tOFF) Switching Transient17 DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current POWER SUPPLY Positive Supply Current (+12 V) Positive Supply Current (+12 V) Negative Supply Current (-12 V) Negative Supply Current (-12 V) Power Supply Rejection Ratio ( VS = 12 V 5%) Power Dissipation ( 12 V)l8
( VS =
12 V
5%; CL = 10 pF; RL = 2 k , unless otherwise noted)
COMMERCIAL 0 C to +70 C AD9300KQ/KP Typ 3 75 15 3.0 2 16 0.990 0.985 0.994 0.01 0.05 0.1 350 27 2 5 9 170 215 70 <0.1 <10 0.03 0.01 68 70 72 76 40 35 35 35 60 2 0.8 5 1 13 13 12.5 12.5 75 306 16 16 15 16 50 45 45 45 15 34 0.1 0.3
Temp +25C Full Full +25C Full +25C +25C +25C +25C Full +25C +25C +25C +25C +25C Full +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C Full Full Full Full +25C Full +25C Full Full +25C
Test Level I VI V I VI V V V I VI V I I V I VI V IV, V I IV V V IV IV IV IV I I I I V VI VI VI VI I VI I VI VI V
Min
Max 10 14 37 55
Units mV mV V/C A A M pF V rms V/V V/V % dB dB MHz MHz V mA V/s ns % % % dB dB ns ns ns ns mV V V A A mA mA mA mA dB mW
100
0.1 0.1
67
-2-
REV. A
AD9300
NOTES 11 Permanent damage may occur if any one absolute maximum rating is exceeded. Functional operation is not implied, and device reliability may be impaired by exposure to higher-than-recommended voltages for extended periods of time. 12 Measured at extremes of temperature range. 13 Measured as slope of VOUT versus VIN with VIN = 1 V. 14 Measured as worst deviation from endpoint fit with V IN = 1 V. 15 Full Power Bandwidth (FPBW) based on Slew Rate (SR). FPBW = SR/2 VPEAK 16 Measured between 20% and 80% transition points of 1 V output. 17 T-Step = Sin2 x Step, when Step between 0 V and +700 mV points has 10% to 90% risetime = 125 ns. 18 Measured with a pulse input having slew rate >250 V/s. 19 Measured at output between 0.28 V dc and 1.0 V dc with V IN = 284 mV p-p at 3.58 MHz and 4.43 MHz. 10 This specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and 10 MHz 2 V p-p signal applied to remaining three channels. If selected channel is grounded through 75 , value is approximately 6 dB higher. 11 This specification is critically dependent on circuit layout. Value shown is measured with selected channel grounded and 10 MHz 2 V p-p signal applied to one other channel. If selected channel is grounded through 75 , value is approximately 6 dB higher. Minimum specification in ( ) applies to DIPs. 12 Consult system timing diagram. 13 Measured from address change to 90% point of -2 V to +2 V output LOW-to-HIGH transition. 14 Measured from address change to 90% point of +2 V to -2 V output HIGH-to-LOW transition. 15 Measured from 50% transition point of ENABLE input to 90% transition of 0 V to -2 V and 0 V to +2 V output. 16 Measured from 50% transition point of ENABLE input to 10% transition of +2 V to 0 V and -2 V to 0 V output. 17 Measured while switching between two grounded channels. 18 Maximum power dissipation is a package-dependent parameter related to the following typical thermal impedances: 16-Pin Ceramic JA = 87C/W; JC = 25C/W 20-Pin LCC JA = 74C/W; JC = 10C/W 20-Pin PLCC JA = 71C/W; JC = 26C/W Specifications subject to change without notice.
Supply Voltages ( VS) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Analog Input Voltage Each Input (IN1 thru IN4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 V Differential Voltage Between Any Two Inputs (IN1 thru IN4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V Digital Input Voltages (A0, A1, ENABLE) . . . -0.5 V to +5.5 V Output Current Sinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0 mA Sourcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0 mA Operating Temperature Range AD9300KQ/KP . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +175C Lead Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . +300C
ABSOLUTE MAXIMUM RATINGSl
EXPLANATION OF TEST LEVELS
Test Level I Test Level II
- -
Test Level III - Test Level IV - Test Level V - Test Level VI -
100% production tested. 100% production tested at +25C, and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. All devices are 100% production tested at +25C. 100% production tested at temperature extremes for military temperature devices; sample tested at temperature extremes for commercial/industrial devices.
ORDERlNG GUlDE
Device
AD9300KQ AD9300TE/883B2 AD9300TQ/883B2 AD9300KP
Temperature Range
0C to +70C -55C to +125C -55C to +125C 0C to +70C
Description
16-Pin Cerdip, Commercial 20-Pin LCC, Military Temperature 16-Pin Cerdip, Military Temperature 20-Pin PLCC, Commercial
Package Option1
Q-16 E-20A Q-16 P-20A
NOTES 1 E = Ceramic Leadless Chip Carrier; P = Plastic Leaded Chip Carrier; Q = Cerdip. 2 For specifications, refer to Analog Devices Military Products Databook.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9300 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
AD9300
AD9300 BURN-IN DIAGRAM SUGGESTED LAYOUT OF AD9300 PC BOARD
FUNCTIONAL DESCRIPTION Four analog input channels. IN1-IN4 GROUND Analog input shielding grounds, not internally connected. Connect each to external low-impedance ground as close to device as possible. One of two TTL decode control lines required for channel selection. See Logic Truth Table. One of two TTL decode control lines required for channel selection. See Logic Truth Table. TTL-compatible chip enable. In enabled mode (logic HIGH), output signal tracks selected input channel; in disabled mode (logic LOW), output is high impedance and no signal appears at output. Negative supply voltage; normally -10 V dc to -15 V dc. Positive supply voltage; normally +10 V dc to +15 V dc. Analog output. Tracks selected input channel when enabled. Bypass terminal for internal bias line; must be decoupled externally to ground through 0.1 F capacitor. Analog signal and power supply ground return. METALIZATION PHOTOGRAPH
A0 A1 ENABLE
-VS +VS OUTPUT BYPASS
GROUND RETURN
Die Dimensions . . . . . . . . . . . . . . . . . 84 x 104 x 18 (max) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 x 4 (min) mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic Bond Wire . . . . . . . . 1.25 mil, Aluminum; Ultrasonic Bonding or 1 mil, Gold; Gold Ball Bonding
MECHANICAL INFORMATION
LOGIC TRUTH TABLE
ENABLE 0 1 1 1 1
AD9300 Timing Diagram
A1 X 0 0 1 1
A0 X 0 1 0 1
OUTPUT High Z IN1 IN2 IN3 IN4 REV. A
-4-
AD9300
THEORY OF OPERATION
Refer to the functional block diagram of the AD9300. As shown in the drawing, this diagram is based on the pinouts of the DIP packaging of the models AD9300KQ and AD9300TQ. The AD9300KP and AD9300TE are packaged in 20-pin surface mount packages. The extra pins are used for ground connections; the theory of operation remains the same. The AD9300 Video Multiplexer allows the user to connect any one of four analog input channels (IN1-IN4) to the output of the device and to switch between channels at megahertz rates. The input channel, which is connected to the output is determined by a 2-bit TTL digital code applied to A0 and A1. The selected input will not appear at the output unless a digital "1" is also applied to the ENABLE input pin; unless the output is enabled, it is a high impedance. Necessary combinations to accomplish channel selection are shown in the Logic Truth Table.
Bipolar construction used in the AD9300 ensures that the input impedance of the device remains high and will not vary with power supply voltages. This characteristic makes the AD9300, in effect, a switchable-input buffer. An onboard bias network makes the performance of the AD9300 independent of applied supply voltages, which can have any nominal value from 10 V dc to 15 V dc. Although the primary application for the AD9300 is the routing of video signals, the harmonic and dynamic attributes of the device make it appropriate for other applications. The AD9300 has exceptional performance when switching video signals and can also be used for switching other analog signals requiring greater dynamic range and/or precision than those in video. As shown in Figure 1, each analog input is connected to the base of a bipolar transistor. If Channel 1 is selected, a current switch is closed and routes current through the input transistor for Channel 1. If Channel 2 is then selected by the digital inputs, the current switch for Channel 1 is opened and the current switch for Channel 2 is closed. This causes current to be routed away from the Channel 1 transistor and into the Channel 2 input transistor. Whenever a channel's input device is carrying current, the analog input applied to that channel is passed to the output stage. The operation of the output stage is similar to that of the input stages. Whenever the output stage is enabled with a HIGH digital "1" signal at the ENABLE pin, the output transistor will carry current and pass the selected analog input. When the output stage is disabled (by virtue of the ENABLE pin being driven LOW with a digital "0"), the output current switch is opened. This routes the current to other circuits within the AD9300 that keep the output transistor biased "off." These circuits require approximately 1 A of bias current from the load connected to the output of the multiplexer. In the absence of a terminating load and the resulting dc bias, the output of the AD9300 "floats" at -2.5 V. In summary, when the AD9300 is enabled by the ENABLE pin being driven HIGH with a digital "1," the selected analog input channel acts as a buffer for the input and the output of the multiplexer is a low impedance. When the AD9300 is disabled with a digital "0" LOW signal, the selected channel acts as an open switch for the input, and the output of the unit becomes a high impedance. This characteristic allows the user to wire-or several AD9300 Analog Multiplexers together to form switch matrices.
Figure 1. Input and Output Equivalent Circuits
REV. A
-5-
AD9300
AD9300 APPLICATIONS
To ensure optimum performance from circuits using the AD9300, it is important to follow a few basic rules that apply to all high speed devices. A large, low-impedance ground plane under the AD9300 is critical. Generally, GROUND and GROUND RETURN connections should be connected solidly to this plane. GROUND pin connections are signal isolation grounds that are not
connected internally; they can be left unconnected, but there may be some degradation in crosstalk rejection. GROUND RETURN, on the other hand, serves as the internal ground reference for the AD9300 and, without exception, should be connected to the ground plane. The output stage of the unit is capable of driving a 2 k 10 pF load. Larger capacitive loads may limit full power bandwidth and increase tOFF (the interval between the 50% point of the ENABLE high-to-low transition and the instant the output becomes a high impedance). For applications such as driving cables (see Figure 2), output buffers are recommended. It is recommended that the AD9300 be soldered directly into circuit boards rather than using socket assemblies. If sockets must be used, individual pin sockets are preferred rather than a socket assembly. A second requirement for proper high speed design involves decoupling the power supply and internal bias supply lines from ground to improve noise immunity. Chip capacitors are recommended for connecting 0.1 F and 0.01 F capacitors between ground and the VS supplies (Pins 9 and 14) and the BYPASS connection (Pin 15).
Figure 2. 4 x 1 AD9300 Multiplexer with Buffered Output Driving 75 Coaxial Cable
Figure 3. Harmonic Distortion vs. Frequency
Figure 4. Output vs. Frequency
Figure 5. Crosstalk vs. Frequency
Figure 6. Test Circuit for Harmonic Distortion, Pulse Response, T-Step Response and Disable Characteristics
Figure 7. Crosstalk Rejection Test Circuit
-6-
REV. A
AD9300
Figure 8. Pulse Response
Figure 9. T-Step Response
Figure 10. Enable to Channel "Off" Response
CROSSPOINT CIRCUIT APPLICATIONS
Four AD9300 multiplexers can be used to implement an 8 x 2 crosspoint, as shown in Figure 11. The circuit is modular in concept, with each pair of multiplexers (#1 and #2; #3 and #4) forming an 8 x 1 crosspoint. When the inputs to all four units are connected as shown, the result is an 8 x 2 crosspoint circuit.
The truth table describes the relationships among the digital inputs (D0-D5) and the analog inputs (S1-S8) and which signal input is selected at the outputs (OUT1 and OUT2). The number of crosspoint modules that can be connected in parallel is limited by the drive capabilities of the input signal sources. High input impedance (3 M) and low input capacitance (2 pF) of the AD9300 help minimize this limitation.
8 2 Crosspoint Truth Table
D2 or D5 0 0 0 0 1 1 1 1
D1 or D4 0 0 1 1 0 0 1 1
D0 or D3 0 1 0 1 0 1 0 1
OUT1 or OUT2 S1 S2 S3 S4 S5 S6 S7 S8
Adding to the number of inputs applied to each crosspoint module is simply a matter of adding AD9300 multiplexers in parallel to the module. Eight devices connected in parallel result in a 32 x 1 crosspoint, which can be used with input signals having 30 MHz bandwidth and 1 V peak-to-peak amplitude. Even more AD9300 units can be added if input signal amplitude and/or bandwidth are reduced; if they are not, distortion of the output signals can result. When an AD9300 is enabled, its low output impedance causes the "off" isolation of disabled parallel devices to be greater than the crosstalk rejection of a single unit.
Figure 11. 8 x 2 Signal Crosspoint Using Four AD9300 Multiplexers
REV. A
-7-
AD9300
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Cerdip (Q) Package
20-Pin LCC (E) Package
C1184a-21-11/90
20-Pin PLCC (P) Package
-8-
REV. A
PRINTED IN U.S.A.

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